Related: As the technology world demands more and more powerful RAM with each new generation of production nodes, DRAM chips must follow 3D NAND and work vertically. Lam Research proposes some novel approaches to achieve this crucial but very complex (and likely expensive) goal.
Lam Research is a California-based company with a mission to advance breakthroughs in semiconductors that can define “the next generation” of the technology world. One of the breakthroughs Lam is considering is 3D, or vertically stacked DRAM memory chips, which the company expects will evolve from traditional 2D chips in five to eight years “based on current technological capabilities.”
lamb recently explained that the industry needs a plan to facilitate this crucial evolutionary step. To envision this “untested future” of DRAM technology, the company leveraged its SEMulator3D software, which is typically used to “virtually fabricate” semiconductor devices by mimicking wafer fabrication. A 3D DRAM architecture must address multiple issues related to scaling, stacking, space shrinkage, and more.
The SEMulator3D design process included the three main components of a traditional DRAM structure, which Lam says includes a bitline that conducts the electrical current that is injected into a transistor. The transistor acts as a gate to maintain (turn on) or stop (turn off) the flow of current in the device. Finally, a capacitor stores the above current in bit form (0 or 1).
lamb tried a few “tricks” to create a new, vertically aligned DRAM architecture by mixing these three main components a bit. The company’s engineers attempted to route the bitline across the opposite side of the transistor to allow room for additional transistors to be connected to the bitline itself and for improved chip density.
They also used novel, state-of-the-art manufacturing techniques such as gate-all-around transistor design. Finally, the Lam researchers increased the number of transistors/capacitors per individual bitline contact by placing transistors on either side of the contact. The resulting “reconfigured” nanosheet can be virtually stacked in a 3D-like DRAM structure.
The first iteration of Lam’s 3D virtual DRAM includes 28 layers of memory cells and would require a manufacturing process two nodes ahead of those used today. The stacked memory cells can be connected in a through-chip via array, which is already possible with NAND flash memory chips.
An alternative, NAND-like approach to fabricating 3D DRAM chips was recently proposed by NEO Semiconductor, who described their 3D X-DRAM invention as a low-cost and scalable solution.